This invention relates to a semiconductor memory device and more particularly to a semiconductor memory device incorporating an error self-correcting circuit.
Recent developments in the semiconductor memory device technology has resulted in a remarkable reduction in the size of a memory cell.
The miniaturization of the memory cell has led to reduction in the quantity of the stored charge, and this has made alpha-induced soft-errors a serious problem. Moreover, a power supply voltage drop is also expected when the internal electric field of the miniaturized device is optimized. Thus, it becomes extremely difficult to secure soft-error resistance such as is presently available in the case of semiconductor memories having larger storage capacities.
Methods of solving this problem and allowing a semiconductor memory to have a larger capacity include incorporating into the memory an error self-correcting circuit for automatically checking and correcting soft-errors within the memory chip. One such method is the multi cell 1-bit method wherein a plurality of memory cells are assigned to store one bit of information to mask the soft-error generated in one cell. Another is the method wherein error-correcting codes are used. In view of the circuit scale additionally necessary for correcting errors, the method employing error-correcting codes is deemed a promising one.
According to a proposed error correction method, a check cell array is provided in addition to a normal memory cell array. An error-correcting circuit receives read-out signals from the memory cell array and the check cell array to generate a correcting signal, which is used for correcting the data to the read-out. The disadvantage of such a conventional semiconductor memory device having an error self-correcting circuit is that the access time as a whole tends to become longer because it takes a significant amount of time to generate the correcting signal in the correcting circuit. The larger the scale of the memory, the greater the number of data bits applied to the correcting circuit and the greater the number of checking bits applied thereto. Accordingly, the time required to correct errors increases, which makes it impossible to read and write data at a high speed, constituting a significant shortcoming of such prior devices.